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Freescale Semiconductor Technical Data
Document Number: MC33290 Rev 8.0, 8/2008
ISO K Line Serial Link Interface
The 33290 is a serial link bus interface device designed to provide bi-directional half-duplex communication interfacing in automotive diagnostic applications. It is designed to interface between the vehicle's on-board microcontroller and systems off-board the vehicle via the special ISO K line. The 33290 is designed to meet the Diagnostic Systems ISO9141 specification. The device's K line bus driver's output is fully protected against bus shorts and overtemperature conditions. The 33290 derives its robustness to temperature and voltage extremes by being built on a SMARTMOS process, incorporating CMOS logic, bipolar/MOS analog circuitry, and DMOS power FETs. Although the 33290 was principally designed for automotive applications, it is suited for other serial communication applications. It is parametrically specified over an ambient temperature range of -40C TA 125C and 8.0 V VBB 18 V supply. The economical SO-8 surface-mount plastic package makes the 33290 very cost effective. Features * * * * * * * * * * *
33290
ISO9141 PHYSICAL INTERFACE
D SUFFIX EF SUFFIX (PB-FREE) 98ASB42564B 8-PIN SOICN
ORDERING INFORMATION
Temperature Range (TA) -40 to 125C Package
Device Operates Over Wide Supply Voltage of 8.0 to 18V Operating Temperature of -40 to 125C MC33290D/R2 Interfaces Directly to Standard CMOS Microprocessors MCZ33290EF/R2 ISO K Line Pin Protected Against Shorts to Ground Thermal Shutdown with Hysteresis ISO K Line Pin Capable of High Currents ISO K Line Can Be Driven with up to 10 nF of Parasitic Capacitance 8.0 kV ESD Protection Attainable with Few Additional Components Standby Mode: No VBat Current Drain with VDD at 5.0 V Low Current Drain During Operation with VDD at 5.0 V Pb-Free Packaging Designated by Suffix Code EF
8-SOICN
+VBAT VDD
33290
VDD MCU Dx SCIR D x SCITx D CEN RX TX ISO GND VDD VBB ISO K-Line T xD R xD
Figure 1. 33290 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products.
(c) Freescale Semiconductor, Inc., 2006-2008. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VBB 1 50 V
3.0 k 20 V 200 10 V 10 V RX 6 ISO 4
Master Bias CEN 8 VDD 7 TX 5
RHys
40 V 125 k Thermal Shutdown 125 k 10 V 2.0 k 10 V GND 3
Figure 2. 33290 Simplified Block Diagram
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Analog Integrated Circuit Device Data Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
VBB NC GND ISO
1 1 2 2 3 3 4 4
88 77 66 55
CEN VDD RX TX
Figure 3. 33290 Pin Connections Table 1. 33290 Pin Definitions
Pin Number 1 2 3 4 5 6 7 8 Pin Name VBB NC GND ISO TX RX VDD CEN Definition Battery power through external resistor and diode. Not to be connected. (1) Common signal and power return. Bus connection. Logic level input for data to be transmitted on the bus. Logic output of data received on the bus. Logic power source input. Chip enable. Logic "1" for active state. Logic "0" for sleep state.
Notes 1. NC pins should not have any connections made to them. NC pins are not guaranteed to be open circuits.
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Rating VDD DC Supply Voltage VBB Load Dump Peak Voltage ISO Pin Load Dump Peak Voltage ISO Short Circuit Current Limit ESD Voltage
(3) (2)
Symbol VDD VBB(LD) VISO IISO(LIM) VESD1 VESD2 Eclamp Tstg TC TJ PD
Value -0.3 to 7.0 45 40 1.0
Unit V V V A V
Human Body Model (4) Machine Model (4) ISO Clamp Energy (5) Storage Temperature Operating Case Temperature Operating Junction Temperature Power Dissipation TA = 25C Peak Package Reflow Temperature During Reflow Thermal Resistance Junction-to-Ambient
(6) (7)
2000 200 10 -55 to +150 -40 to +125 -40 to +150 mJ C C C W 0.8 C C/W 150
,
TPPRT RJA
Note 7.
Notes 2. Device will survive double battery jump start conditions in typical applications for 10 minutes duration, but is not guaranteed to remain within specified parametric limits during this duration. 3. ESD data available upon request. 4. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). 5. 6. 7. Nonrepetitive clamping capability at 25C. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions of 4.75 V VDD 5.25 V, 8.0 V VBB 18 V, -40C TC 125C, unless otherwise noted.
Characteristic POWER AND CONTROL VDD Sleep State Current Tx = 0.8 VDD, CEN = 0.3 VDD VDD Quiescent Operating Current Tx = 0.2 VDD, CEN = 0.7 VDD VBB Sleep State Current VBB = 16 V, Tx = 0.8 VDD, CEN = 0.3 VDD VBB Quiescent Operating Current TX = 0.2 VDD, CEN = 0.7 VDD Chip Enable Input High-Voltage Threshold Input Low-Voltage Threshold
(8) (9)
Symbol
Min
Typ
Max
Unit
IDD(SS)
mA
-
IDD(Q)
- - - - - - - -
0.1 mA
-
IBB(SS)
1.0 A
-
IBB(Q)
50 mA
-
VIH(CEN) VIL(CEN) IPD(CEN) VIL(Tx) 0.7 VDD
1.0 V
-
0.3 VDD 40 A V
-
2.0
Chip Enable Pull-Down Current (10) TX Input Low-Voltage Threshold RISO = 510 (11) TX Input High-Voltage Threshold RISO = 510
(12)
-
VIH(Tx) 0.7 x VDD IPU(Tx) VOL(Rx) -40
0.3 x VDD V
- -
-
-2.0 A V
TX Pull-Up Current (13) RX Output Low-Voltage Threshold RISO = 510 , TX = 0.2 VDD, Rx Sinking 1.0 mA RX Output High-Voltage Threshold RISO = 510 , TX = 0.8 VDD, RX Sourcing 250 A Thermal Shutdown (14)
-
VOH(Rx) 0.8 VDD TLIM 150
- -
170
0.2 VDD V
- -
C
Notes 8. When IBB transitions to >100 A. 9. When IBB transitions to <100 A. 10. Enable pin has an internal current pull-down. Pull-down current is measured with CEN pin at 0.3 VDD. 11. 12. 13. 14. Measured by ramping TX down from 0.7 VDD and noting TX value at which ISO falls below 0.2 VBB. Measured by ramping TX up from 0.3 VDD and noting the value at which ISO rises above 0.9 VBB. Tx pin has internal current pull-up. Pull-up current is measured with TX pin at 0.7 VDD. Thermal Shutdown performance (TLIM) is guaranteed by design but not production tested.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (Continued) Characteristics noted under conditions of 4.75 V VDD 5.25 V, 8.0 V VBB 18 V, -40C TC 125C, unless otherwise noted.
Characteristic ISO I/O Input Low Voltage Threshold RISO = 0 , TX = 0.8 VDD
(15)
Symbol
Min
Typ
Max
Unit
VIL(ISO) - VIH(ISO) 0.7 x VBB VHys(ISO) IPU(ISO) -5.0 ISC(ISO) 50 VOL(ISO) - VOH(ISO) 0.95 x VBB - - - 0.1 x VBB - 1000 - -140 0.05 x VBB - - - 0.1 x VBB - 0.4 x VBB
V
Input High Voltage Threshold RISO = 0 , TX = 0.8 VDD (16) Input Hysteresis (17) Internal Pull-Up Current RISO = , TX = 0.8 VDD, VISO = 9.0 V, VBB = 18 V Short Circuit Current Limit (18) RISO = 0 , TX = 0.4 VDD, VISO = VBB Output Low Voltage RISO = 510 , TX = 0.2 VDD Output High Voltage RISO = , TX = 0.8 VDD
V
V A
mA
V
V
Notes 15. ISO ramped from 0.8 VBB to 0.4 VBB, Monitor RX, Value of ISO voltage at which RX transitions to 0.3 VDD. 16. 17. 18. ISO ramped from 0.4 VBB to 0.8 VBB, Monitor RX, Value of ISO voltage at which RX transitions to 0.7 VDD. Input Hysteresis, VHys(ISO) = VIH(ISO) - VIL(ISO). ISO has internal current limiting.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions of 4.75 V VDD 5.25 V, 8.0 V VBB 18 V, -40C TC 125C, unless otherwise noted.
Characteristic Fall Time (19) RISO = 510 to VBB, CISO = 10 nF to Ground ISO Propagation Delay (20) High to Low: RISO = 510 , CISO = 500 pF (21) Low to High: RISO = 510 , CISO = 500 pF (22) Notes 19. Time required ISO voltage to transition from 0.8 VBB to 0.2 VBB. 20. 21. 22. Changes in the value of CISO affect the rise and fall time but have minimal effect on Propagation Delay. Step TX voltage from 0.2 VDD to 0.8 VDD. Time measured from VIH(ISO) until VISO reaches 0.3 VBB. Step TX voltage from 0.8 VDD to 0.2 VDD. Time measured from VIL(ISO) until VISO reaches 0.7 VBB. tPD(ISO) - - - - 2.0 2.0 Symbol tfall(ISO) - - 2.0 s Min Typ Max Unit s
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Analog Integrated Circuit Device Data Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS ELECTRICAL PERFORMANCE CURVES
ELECTRICAL PERFORMANCE CURVES
VIL and VIH, INPUT THRESHOLD (RA-
VOL and VOH, ISO OUTPUT (RATIO)
0.6 VIH; VDD = 5.25 V, VBB = 18 V VIH; VDD = 4.75 V, VBB = 8.0 V
1.2 1.0 0.8 0.6 0.4 0.2 VOL 0 -50 0 50 100 150 VDD = 4.75 V, VBB = 8.0 V and VDD = 5.25 V, VBB = 18 V VOH
0.575 0.55
0.525 0.5 VIL; VDD = 5.25 V, VBB = 18 V VIL; VDD = 4.75 V, VBB = 8.0 V 0 50 100 150 TA, AMBIENT TEMPERATURE (C)
0.475 -50
TA, AMBIENT TEMPERATURE (C)
Figure 4. ISO Input Threshold/VBB vs. Temperature
Figure 6. ISO Fall Time vs. Temperature
tPD(ISO), PROPAGATION DELAY (s)
0.95 tfall(ISO), ISO FALL TIME (s) 0.9 0.85 0.8 0.75 VDD = 4.75 V, VBB = 8.0 V 0.7 0.65 -50
0.7 VDD = 5.25 V, VBB = 18 V 0.6 VDD = 4.75 V, VBB = 8.0 V 0.5 0.4 0.3 0.2 -50 PdH-L
VDD = 5.25 V, VBB = 18 V
VDD = 5.25 V, VBB = 18 V 0 50 100
PdL-H VDD = 4.75 V, VBB = 8.0 V 150
0
50
100
150
TA, AMBIENT TEMPERATURE (C)
TA, AMBIENT TEMPERATURE (C)
Figure 5. ISO Output/VBB vs. Temperature
Figure 7. ISO Propagation Delay vs. Temperature
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TYPICAL APPLICATIONS INTRODUCTION
TYPICAL APPLICATIONS
INTRODUCTION
The 33290 is a serial link bus interface device conforming to the ISO 9141 physical bus specification. The device was designed for automotive environment usage compliant with On-Board Diagnostic (OBD) requirements set forth by the California Air Resources Board (CARB) using the ISO K line. The device does not incorporate an ISO L line. It provides bidirectional half-duplex communications interfacing from a microcontroller to the communication bus. The 33290 incorporates circuitry to interface the digital translations from 5.0 V microcontroller logic levels to battery level logic and from battery level logic to 5.0 V logic levels. The 33290 is built using Freescale Semiconductor's SMARTMOS process and is packaged in an 8-pin plastic SOIC.
FUNCTIONAL DESCRIPTION
The 33290 transforms 5.0 V microcontroller logic signals to battery level logic signals and visa versa. The maximum data rate is set by the fall time and the rise time. The fall time is set by the output driver. The rise time is set by the bus capacitance and the pull-up resistors on the bus. The fall time of the 33290 allows data rates up to 150 kbps using a 30 percent maximum bit time transition value. The serial link interface will remain fully functional over a battery voltage range of 6.0 to 18 V. The device is parametrically specified over a dynamic VBB voltage range of 8.0 to 18 V. Required input levels from the microcontroller are ratiometric with the VDD voltage normally used to power the microcontroller. This enhances the 33290's ability to remain in harmony with the RX and TX control input signals of the microcontroller. The RX and TX control inputs are compatible with standard 5.0 V CMOS circuitry. For fault-tolerant purposes the TX input from the microcontroller has an internal passive pull-up to VDD, while the CEN input has an internal passive pull-down to ground. A pull-up to battery is internally provided as well as an active data pull-down. The internal active pull-down is current-limit-protected against shorts to battery and further protected by thermal shutdown. Typical applications have reverse battery protection by the incorporation of an external 510 pull-up resistor and diode to battery. Reverse battery protection of the device is provided by using a reverse battery blocking diode ("D" in the Simplified Application Diagram on page 1). Battery line transient protection of the device is provided for by using a 45 V zener and a 500 resistor connected to the VBB source as shown in the same diagram. Device ESD protection from the communication lines exiting the module is through the use of the capacitor connected to the VBB device pin and the capacitor used in conjunction with the 27 V zener connected to the ISO pin.
33290
Analog Integrated Circuit Device Data Freescale Semiconductor
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PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the "98A" listed below.
D SUFFIX EF SUFFIX (PB-FREE) 8-PIN PLASTIC PACKAGE 98ASB42564B REV. U
33290
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Analog Integrated Circuit Device Data Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION 6.0
DATE 7/2006
DESCRIPTION OF CHANGES
7.0
10/2006
8.0
8/2008
Implemented Revision History page Converted to Freescale format and updated to the prevailing for and style Added Pb-free suffix EF Removed MC33290EG/R2 and replaced with MCZ33290EG/R2 in the Ordering Information block * Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Ratings on page 4. Added note with instructions to obtain this information from www.freescale.com. * Corrected the Document header information. * Updated to the current Freescale form and style.
* * * *
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Analog Integrated Circuit Device Data Freescale Semiconductor
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MC33290 Rev 8.0 8/2008

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